1. Field of the Invention
The present disclosure relates to high voltage generating circuits and, more particularly, to high voltage generating circuits for generating voltages higher than a power supply voltage, and semiconductor memory devices having the same.
2. Description of the Related Art
In general, a cell access transistor connected to a word line of a semiconductor memory device includes a Negative-Channel Metal Oxide Semiconductor (NMOS) transistor. If a power voltage level is applied to a word line when data are written to a cell or when data stored in a cell are read, data of “high” level of a bit line is reduced in level by a threshold voltage of the NMOS transistor and then stored in a cell, and data of “high” level stored in a cell is reduced in level by a threshold voltage of the NMOS transistor and then transmitted to a bit line.
For the foregoing reason, a semiconductor memory device includes a high voltage generating circuit to apply a higher voltage than a power supply voltage to a word line, such that data of “high” level can be transmitted without a level loss.
There is a tendency for a power voltage level of a semiconductor memory device to be lowered. In addition, a small row cycle time is required for a high speed operation. However, a high voltage and a threshold voltage of the NMOS transistor are not lowered in proportion to a level drop of a power voltage. In order to pump a desired high voltage level, the number of pumping times of a high voltage generating circuit should be increased, whereby a pumping cycle time should be extended. However, the extended pumping cycle time leads to an extended row cycle time. This makes it difficult to configure a high speed semiconductor memory device.
FIG. 1 is a block diagram illustrating a conventional high voltage generating circuit, indicated generally by the reference numeral 100. The semiconductor memory device of FIG. 1 includes a pumping driving signal generating circuit 10, a pumping control signal generating circuit 12, and a pumping circuit 14. Functions of the components of the high voltage generating circuit of FIG. 1 are explained below.
The pumping driving signal generating circuit 10 generates a pumping driving signal BACT with a pumping cycle time when a bank selecting signal BA is generated. The pumping control signal generating circuit 12 generates pumping control signals CON1˜n in response to the pumping driving signal BACT. The pumping circuit 14 operates to pump a high voltage VPP level in response to the pumping control signals CON1˜n. In general, one high voltage generating circuit of FIG. 1 is provided for each of cell array banks of a semiconductor memory device.
FIG. 2 is a circuit diagram illustrating the pumping driving signal generating circuit of the high voltage generating circuit of FIG. 1, indicated generally by the reference numeral 200. The pumping driving signal generating circuit of FIG. 2 includes inverters I1 to I4, AND gates AND1 and AND2, and a D flip-flop DFF1. Functions of the components of the pumping driving signal generating circuit of FIG. 2 are explained below.
A circuit comprised of the AND gate AND1 and the inverter I1 generates a signal, which transits to a “high” level in response to a transition of a clock signal CK to a “high” level in the state that the pumping driving signal BACT maintains a “low” level. The D flip-flop DFF1 is reset to a “low” level during an initialization operation and receives and outputs the bank selecting signal BA when an output signal of the AND gate AND1 transits to a “high” level during a normal operation. A circuit comprised of the inverters I2 to I4 and the AND gate AND2 is a pulse generating circuit, transits the pumping driving signal BACT to a “high” level when an output signal of the D flip-flop DFF1 transits to a “high” level, and maintains a “high” level for a delay time of the inverters I2 and I4, and thereafter, transits the pumping driving signal BACT to a “low” level.
FIG. 3 is a timing diagram illustrating operation of the pumping driving signal generating circuit of FIG. 2, indicated generally by the reference numeral 300, where four memory cell banks are sequentially accessed.
In FIG. 3, a clock signal CK and a command signal COM are signals that are applied from an external portion of the semiconductor memory device. tCK denotes a cycle of the clock signal CK, tRDD denotes a minimum time spent until an active command ACT for accessing another memory cell array banks is accessed after an active command ACT for accessing a certain memory cell array bank is applied, tRC denotes a row cycle time spent until an active command for accessing the same memory cell array bank is applied after an active command ACT for accessing a certain memory cell array bank is applied, and tAKE denotes a pumping cycle time which is a minimum time required to pump a desired high voltage VPP level.
When the clock signal CK and the active command ACT are applied at a time interval tRRD of 2tCK from an external portion and bank addresses for selecting four memory cell banks are sequentially input, bank selecting signals BA1 to BA4 are sequentially generated. So, the pumping driving signal generating circuit of the respective memory cell array banks sequentially generates the pumping driving signals BACT1 to BACT4 which are pulse signals, in response to transition of the bank selecting signals BA1 to BA4 to a “high” level, respectively.
When the interval tRDD is set to 2tCK, a row cycle time tRC should be set to 8tCK. However, since a pumping cycle time tAKE for the high voltage generating circuit to pump a high voltage VPP level is 12tCK, it is impossible to set the row cycle time tRC to 8tCK.
Therefore, the conventional semiconductor memory device has a problem in that a row cycle time tRC cannot be reduced due to a pumping cycle time tAKE and thus a desired high speed operation cannot be achieved.